About this role
Driving technical initiatives for AI supercomputer hardware systems involves overseeing manufacturing, quality, and reliability from the initial concept phase through mass production and deployment. Day-to-day work centers on leading process flows, tooling, fixtures, and assembly operations while collaborating with design engineers, technical program managers, and external vendors to keep hardware delivery on schedule. Professionals in the hardware organization develop AI-native silicon and tightly integrated systems to support advanced workloads and frontier models.
Accountabilities include managing integrated readiness plans across levels like L6, L10, and L11, monitoring supplier scorecards, and guiding root cause investigations for any manufacturing defects. Success in the position requires hands-on experience with high-performance computing hardware, multinational JDM or CM partners, and structured problem-solving frameworks. Ideal candidates handle ambiguity well, communicate cross-functional risks clearly, and maintain deep technical ownership through product release and sustaining operations.
What you will do
- Manage integrated manufacturing and quality readiness across various product levels using established gates, milestones, and deliverables.
- Translate product requirements into qualification plans, process controls, and test acceptance criteria alongside design engineers and subject matter experts.
- Track supplier and line scorecards by analyzing yield, defect tracking, process capability, and reliability data to assess overall health.
- Lead failure analysis, root cause investigations, and corrective actions for development, production, and deployment issues.
- Evaluate manufacturing and quality impacts resulting from design, process, source, or site changes.
- Coordinate risk mitigation and communicate priorities across functional teams to meet strict schedules and quality standards.
What you need
- Demonstrated history of owning manufacturing and quality outcomes for complex hardware from new product introduction through mass production.
- Familiarity with high-performance computing hardware risks across component, system, and rack integration.
- Experience building integrated readiness plans and managing qualification gates and dependencies.
- Background working alongside multinational JDM or CM partners on process controls, yield improvement, and quality audits.
- Proficiency in mechanical and electrical design principles such as DFM, DFA, DFT, and DFR.
- Experience applying structured problem-solving methodologies like 8D, 5 Whys, and fishbone analysis.
Benefits
- Offers Equity
- Relocation assistance to new employees
Questions candidates ask
Where is the position located and what is the remote work policy?
This role is based in San Francisco, CA. The team uses a hybrid work model requiring 3 days in the office per week.
What is the compensation range for the role?
The salary ranges from $123K to $285K and includes offered equity.
What level of manufacturing and quality ownership is expected?
The person in this role owns the integrated manufacturing and quality readiness for a product across L6, L10, and L11, with clear gates, milestones, deliverables, owners, and closure criteria. They also lead readiness of process flows, tooling, fixtures, assembly operations, test interfaces, and production controls.