About this role
Engineers who thrive on building custom silicon to support massive workloads will find a natural home in this role. OpenAI's hardware organization develops AI-native silicon and tightly integrated systems, building on initiatives like Jalapeño to power future frontier models by co-designing chips, systems, tools, and methodologies.
The physical design engineer will own the implementation of floorplan blocks from initial planning to final signoff, shape power, performance, and area trade-offs, and develop automated design flows. This individual contributor position exists to deliver optimized datapath and interconnect solutions for next-generation AI accelerators, directly impacting silicon performance, cost efficiency, and team execution velocity.
What you will do
- Develop, build, and own tools, flows, and methodologies specifically for physical implementation.
- Manage the physical implementation of floorplan blocks starting from floorplanning through to final signoff.
- Partner closely with RTL designers to drive optimal block implementation solutions.
- Analyze and optimize designs for timing, power, and area trade-offs in cooperation with EDA vendors and ASIC partners.
What you need
- Possess a BS with four or more years, an MS with two or more years, or a PhD with zero to one year of relevant industry experience in physical design and methodology development.
- Demonstrate prior success in taping out complex silicon designs.
- Bring hands-on experience with block physical implementation and PPA convergence.
- Demonstrate strong coding experience using Python, Bazel, and Tcl.
- Show strong experience in building physical design tools, flows, and methodologies.
- Maintain a strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification, and timing closure.
- Hold deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC, and power estimation.
Nice to have
- Experience with AI or HPC-focused chips
- Experience with optimizing PPA for high performance compute cores
- Hands-on experience with top-level design methodologies
Benefits
- Offers Equity
Skills and tech stack
Questions candidates ask
What compensation and equity is included for this role?
The salary ranges from $266K to $445K and the position includes offers of equity.
Where is the hardware organization located?
The role is based in San Francisco.
What are the legal status requirements for applicants?
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.