AI Silicon, DFT Engineer
About this role
The team at Unconventional is building a novel computing platform designed to achieve a thousandfold increase in AI efficiency by mapping neural networks directly to semiconductor physics. As a DFT Engineer, this person will lead the implementation of comprehensive test architectures, handle hierarchical DFT methodologies for large-scale system-on-chip designs, and ensure the testability of complex digital logic and custom mixed-signal blocks. The role exists to turn novel artificial intelligence concepts into high-performance, energy-efficient hardware by taking ownership of testability realization and yield improvements. A strong candidate will be someone with extensive background in digital design and test architecture who thrives in a multi-disciplinary research and development environment.
Working on advanced hardware requires driving bottom-up hierarchical DFT methodologies, managing core-level test wrapping, and overseeing foundry interfaces to analyze defect densities. The professional in this position will also tackle test strategies for 2.5D and 3D multi-stacked die packaging, optimize power, performance, and area metrics, and handle final DFT sign-off processes including automatic test pattern generation and fault simulation. Anyone who excels at solving complex hardware challenges and wants to redefine foundational computing architectures will find this opportunity rewarding.
What you will do
- Lead the implementation of comprehensive test architectures utilizing industry-standard computer-aided design tools for scan compression, memory built-in self-test, and boundary scan logic.
- Drive bottom-up hierarchical design-for-test methodologies for large-scale system-on-chip designs by managing core-level test wrapping, pattern retargeting, and top-level integration.
- Own the overarching testability strategy and collaborate with foundry interfaces to analyze defect densities and improve yields for test chips.
- Develop test methodologies for 2.5D and 3D multi-stacked die packaging while ensuring high test coverage across die-to-die interfaces.
- Work at the interface of digital and analog design to create novel test strategies for custom mixed-signal blocks.
- Drive aggressive test coverage, test time, and yield targets while influencing micro-architecture for better power, performance, and area.
- Own the final testability sign-off process including automatic test pattern generation, vector validation, fault simulation, and timing closure.
What you need
- Hold a Bachelor of Science or Master of Science degree in Electrical Engineering, Computer Engineering, or a related field.
- Bring at least 10 years of industry experience in digital design-for-test and test architecture with a proven track record of successful tapeouts on modern process nodes.
- Possess deep expertise in scan compression, memory built-in self-test generation, fault modeling, and automatic test pattern generation.
- Demonstrate a deep understanding of physical design challenges in advanced nodes and their impact on test reliability.
- Show expert-level mastery of standard electronic design automation tool suites for test implementation and vector generation.
- Apply strong scripting skills in Tcl, Python, or Perl to automate design flows and data analysis.
- Communicate clearly and effectively with experience managing deliverables from external vendors or design houses.
Nice to have
- Hands-on experience with modern die-to-die interconnect test strategies, chiplet testing, and three-dimensional integrated circuit architectures.
- Experience with test architecture for machine learning accelerators or large-scale systolic arrays.
- Experience with top-level integration of large custom analog macros and complex power-sequencing requirements.
- Familiarity with state of the art artificial intelligence tools to accelerate chip design.
Benefits
- Best-in-class health benefits
- 401k matching
- Truly unlimited PTO
- Complimentary meals in the Mountain View office
Skills and tech stack
Questions candidates ask
Where is this job located?
This position is based in Mountain View, California with remote options available.
What is the primary mission of the team?
The team aims to redefine computing for the next 50 years by solving the fundamental energy limitation of artificial intelligence at a global scale. They are building a new foundation for AI that is 1000x more efficient by exploiting semiconductor physics.
What kind of packaging and integration experience is relevant?
Candidates will work on 2.5D and 3D multi-stacked die packaging, utilizing emerging standards like IEEE 1838. Nice-to-have experience includes modern die-to-die interconnect test strategies, chiplet testing, and three-dimensional integrated circuit architectures.
The application is on the official Unconventional, Inc. careers page.
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