Technical Program Manager SOC & Digital Design
About this role
Tenstorrent is seeking a Technical Program Manager for SoC & Digital Design in Tokyo, Japan, to oversee the creation and integration of advanced chiplets supporting machine learning processors and RISC-V CPU servers. This hybrid role is ideal for structured technical leaders with a background in semiconductor engineering and cross-functional program management.
Role Overview
The Technical Program Manager joins the System-on-Chip team in Tokyo to direct complex chiplet development programs, ranging from early architecture to tape-out. This position calls for an organized leader who can manage dependencies, mitigate risks, and guide projects involving memory, I/O functionality, and AI processors. Candidates at various levels of seniority are welcome to apply, with final level and compensation aligned during the evaluation process.
Key Responsibilities
Requirements
Skills and Tools
Salary and Benefits
Tenstorrent provides a highly competitive compensation package and benefits program for qualified personnel.
About the Company
Tenstorrent pushes the boundaries of artificial intelligence technology to improve cost efficiency, performance, and usability. The organization unites diverse experts to build custom RISC-V CPUs from the ground up and design superior AI platforms through curiosity and collaboration.
How to Apply
Interested candidates should visit the official Tenstorrent careers page to submit an application for this hybrid position located in Tokyo.
Questions candidates ask
Where is this job located?
This position is hybrid and based out of Tokyo, Japan.
What experience level is required?
The position requires 5+ years of experience in engineering leadership, technical program management, or SoC chip design, and welcomes candidates at various seniority levels.
What qualifications are needed for the role?
Applicants need a bachelor’s or master’s degree in computer engineering, electrical engineering, or a related field, along with a strong understanding of the chip development lifecycle.
Are there specific technology familiarity requirements?
Candidates should be familiar with industry standards and technologies including RISC-V, AMBA, NoC, Ethernet, and PCIe/CXL.
Why is U.S. export control compliance mentioned?
The role provides access to technology and information subject to U.S. export laws, meaning employment offers may depend on citizenship, permanent residency, or the ability to obtain necessary license approvals.