About this role
Crusoe is seeking a Staff Hardware Systems Engineer in San Francisco to support high-performance compute infrastructure for AI workloads. This full-time role suits experienced professionals with a strong background in hardware validation, debugging, and production support.
Role Overview
The Staff Hardware Systems Engineer joins the Cloud Engineering department at Crusoe to strengthen the Hardware Systems Engineering team. This position focuses on closing critical skill gaps in debugging, validation, and production support of high-performance compute systems. The successful candidate manages the full hardware lifecycle, ranging from prototype bring-up to large-scale production, while driving automation, deep issue resolution, and reliability across GPU- and CPU-based infrastructure.
Key Responsibilities
Requirements
Nice to Have
Skills and Tools
Salary and Benefits
About the Company
Crusoe operates as a vertically integrated AI infrastructure company built to power ambitious AI workloads with an energy-first approach. The company owns and operates each layer of the technology stack from electrons to tokens to make AI infrastructure better for the world and faster for innovators.
How to Apply
Interested candidates should visit the official Crusoe careers page to submit an application for this position.
Skills and tech stack
Questions candidates ask
What is the salary range for the Staff Hardware Systems Engineer role?
The compensation range for this position is between $215,000 and $260,000 per year, with Restricted Stock Units included in all offers.
Where is the position located?
The role is located in San Francisco, California.
What level of experience is required?
Candidates need 8 to 10+ years of experience in hardware development, validation, sustaining engineering, or production engineering.
What educational background is expected?
Applicants should hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or have equivalent experience.
What specific technical domains are central to this role?
The role requires deep expertise in PCIe, InfiniBand, and NVMe storage debugging, along with hardware bring-up, board-level debugging, and system-level validation.
