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CPU Core Design Verification Testbench Lead

TenstorrentAustin, Texas, United States; Santa Clara, California, United StatesRISC V
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Salary
Not listed
Job type
Full-time
Posted
22 May 2026
Status
Open · checked 7d ago

About this role

Role Overview

The CPU Core Design Verification Testbench Lead position at Tenstorrent involves taking charge of CPU core-level testbench development and verification for high-performance out-of-order RISC-V cores. This hybrid role is located in either Austin, Texas or Santa Clara, California, and is well-suited for professionals experienced in digital design and processor verification.

Key Responsibilities

Lead hands-on CPU core-level testbench development for high-performance out-of-order RISC-V cores.
Own and evolve CVM-based verification methodology, infrastructure, and reusable testbench components.
Plan and drive functional verification for CPU core features, ISA behavior, and microarchitectural scenarios.
Develop UVM, assembly, C/C++ stimulus, and C++ functional models for RISC-V extensions and un-core components like APIC and IOMMU.
Debug regressions, close coverage, and improve core, cluster, and chip-level testbenches across simulation, emulation, and post-silicon environments.
Develop testbench and tooling infrastructure that combines Python orchestration with specialized AI agents to accelerate triage and root-cause analysis.

Requirements

Bring 8+ years in CPU verification, CPU testbench development, or closely related digital design.
Possess deep hands-on experience building and owning CPU core-level testbenches from scratch.
Demonstrate an in-depth understanding of high-performance out-of-order CPU microarchitecture.
Feel comfortable developing testbench infrastructure using CVM methodology.
Work effectively across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams.
Utilize AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis with strong engineering judgment.
Must be eligible to access U.S. export-controlled technology in compliance with U.S. export laws and regulations.

Nice to Have

Experience with UVM as a strong plus.

Skills and Tools

Python
C++
CVM methodology
UVM
RTL
RISC-V architecture

About the Company

Tenstorrent leads the industry in cutting-edge artificial intelligence technology by transforming performance expectations, ease of use, and cost efficiency. The diverse team of technologists has developed a high-performance RISC-V CPU entirely from scratch, driven by a shared passion for AI and a commitment to building the best platform possible. Tenstorrent values collaboration, curiosity, and solving difficult problems while creating open, state-of-the-art compute solutions for real workloads and developers.

How to Apply

Candidates should visit the official Tenstorrent careers page to submit an application for this hybrid role.

Skills and tech stack

PythonC++

Questions candidates ask

Where is this job located?

This hybrid role is based out of Austin, Texas or Santa Clara, California.

How many years of experience are required?

Applicants must bring 8+ years of experience in CPU verification, CPU testbench development, or closely related digital design.

What programming languages are needed?

The role requires working with Python and C/C++ for testbench infrastructure, stimulus, and functional models.

Are there specific export control requirements?

Yes, employment is contingent upon the applicant being eligible to access U.S. export-controlled technology due to federal laws and regulations.

What verification methodology is used?

The position centers on owning and evolving CVM-based verification methodology, with UVM experience noted as a strong plus.

Ready to apply?

The application is on the official Tenstorrent careers page.

Apply on company site